The ternary triggers based on binary logical units
The ternary trigger TTBL-22
Usage
Building of ternary logical units (registers, adders, etc.) from binary logical units.
This trigger has 2 logical inputs, a controlling input (reset) and 2 outputs.
Its architecture is made of 2 AND, 2 NOT and 2 OR logical units.
The logic circuit:
Functioning principle:
- The circuit has 3 steady states of output Q+Q- (0,0), Q+Q- (1,0), Q+Q- (0,1)
- Set up of outputs is based on the following rules:
- IF S+S (1,0) THEN outputs are set to Q+Q- (1,0), Here, if we change S+ to 0, then outputs will remain unchanged, that is Q+Q - (1,0);
- IF S+S (0,1) THEN outputs are set to Q+Q- (0,1), Here, if we change S- to 0, then outputs will remain unchanged, that is Q+Q - (0,1);
- IF S+S (1,1) THEN outputs are set to Q+Q- (0,0), Here, if to change S + to 0 and S - to 0 outputs will remain unchanged, that is Q+Q- (0,0);
Advantages:
- The ternary trigger is built on existing binary logical units;
- Simple integration with binary devices;
- Optimal implementation: 1 ternary bit is made from 2 binary bits.
Disadvantages:
- Number of logical units required for ternary trigger is bigger than that required for 2 binary RS triggers
- 2 channels for 1 ternary bit are required
The ternary trigger TTBL-3R2
Usage
Building of ternary logical units (registers, adders, etc.) from binary logical units.
This trigger has 2 logical inputs, a controlling input (reset) and 2 outputs.
Its architecture is made of 4 AND, 3 NOT and 2 OR logical units.
The logic circuit:
Functioning principle:
- The circuit has 3 steady states of output Q+Q - (0,0), Q+Q - (1,0), Q+Q - (0,1)
- Set up of outputs is based on the following rules:
- IF S+S-R (1,0,0) THEN outputs are set to Q+Q - (1,0), Here, if we change S+ to 0, then outputs will remain unchanged, that is Q+Q - (1,0);
- IF S+S-R (0,1,0) THEN outputs are set to Q+Q - (0,1), Here, if we change S- to 0, then outputs will remain unchanged, that is Q+Q - (0,1);
- IF S+S-R (1,1,0) THEN outputs are set to Q+Q - (0,0), Here, if to change S + to 0 and S - to 0 outputs will remain unchanged, that is Q+Q - (0,0);
- IF S+S-R (0,0,1) THEN outputs are set to Q+Q - (0,0), Here, if change R to 0 then outputs will remain unchanged Q+Q - (0,0)
Advantages:
- The ternary trigger is built on existing binary logical units;
- Simple integration with binary devices;
- Optimal implementation: 1 ternary bit is made from 2 binary bits.
Disadvantages:
- Number of logical units required for ternary trigger is bigger than that required for 2 binary RS triggers
- 2 channels for 1 ternary bit are required